SV_SYNTH_SOURCES=system/System.sv
VERILOG_SYNTH_SOURCE=system/System.v

TOP_MODULE_RESOURCE_CHECK=SystemResourceCheck
TOP_MODULE_DEMO=SystemDemo
CONSTRAINTS=../common/constraints/ulx3s.lpf

ZIP_SOURCES=DatapathPipelined.sv ../hw4-multicycle/DividerUnsignedPipelined.sv ../hw2b-cla/cla.sv fpga_build/resource-report.json
ZIP_FILE=pipelined.zip

include ../common/make/fpga.mk

ifndef CLOCK_FREQUENCY
CLOCK_FREQUENCY=20
endif

CLOCK_GEN_NAME=MyClockGen
CLOCK_GEN_FILE=$(CLOCK_GEN_NAME).v

# run ecppll to set clocks
clock-gen: Makefile
	mkdir -p $(BACKEND_OUTPUT_DIR)
	ecppll --internal_feedback --clkin_name input_clk_25MHz --clkin 25 --clkout0_name clk_proc --clkout0 $(CLOCK_FREQUENCY) -n $(CLOCK_GEN_NAME) -f .tmp-clk-gen.v > $(BACKEND_OUTPUT_DIR)/clock_generation_report.txt
	@echo 'check that clocks have the requested frequency'
	-grep "clkout0 frequency: $(CLOCK_FREQUENCY) MHz" $(BACKEND_OUTPUT_DIR)/clock_generation_report.txt
	@echo '//' > $(CLOCK_GEN_FILE) # overwrite existing file
	@echo '// DO NOT EDIT: This file was auto-generated by the ecppll program' >> $(CLOCK_GEN_FILE)
	@echo '//' >> $(CLOCK_GEN_FILE)
	@echo '' >> $(CLOCK_GEN_FILE)
	@echo '`timescale 1ns / 1ns' >> $(CLOCK_GEN_FILE)
	@echo '' >> $(CLOCK_GEN_FILE)
	@cat .tmp-clk-gen.v >> $(CLOCK_GEN_FILE)

# compile demo code and extract into mem_initial_contents.hex
demo-code:
#	cd ledrop-rust && cargo build --release # Rust version
	cd uart-c && $(MAKE) uart.bin  # C version
	python3 make-mem-contents.py